1. Field of the Invention
The present invention relates to memories for integrated circuits and more particularly to Electrically Programmable Read-Only (EPROM) and Electrically Erasable (EEPROM) memory cells.
2. Discussion of the Related Art
FIGS. 1A-1D are schematic cross-sectional views of various known types of memory cells. FIG. 1A represents an EPROM cell that corresponds to a MOS transistor in which a floating gate is interposed between the control gate and the substrate. The EPROM cell includes, in a P-type substrate 1, source and drain N-type regions 2 and 3 having, for example, the so-called LDD shape as represented, that is, lower doped N-type regions are provided on both sides of the channel region. The channel region is coated with a first insulated floating gate GF, in turn coated with a second insulated control gate GC. Conventionally, the source and the substrate are grounded.
To program such a cell, the control gate and the drain are raised to positive voltages, for example, 12 volts and 6 volts, respectively. As a result, a depleted channel region is formed beneath the gate and electrons flow from the source to the drain. A voltage barrier occurs near the drain region and the electron flow in this region generates so-called hot electrons which are injected in the floating gate which is therefore negatively charged.
Thereafter, when an attempt is made to turn on the MOS transistor whose gate is the control gate GC, depending on whether the floating gate GF has been negatively charged or not, a more or less high gate voltage must be applied. The state of a cell can be determined during a read operation by applying a gate voltage such that the non-programmed cells turn conductive and the programmed cells remain blocked. In other words, the "threshold voltage" of the transistor is modified by the above mentioned operation.
The above cell described with relation to FIG. 1A is normally erased by exposure to UV-rays. Then, the electrons gain a sufficient energy to overcome the oxide barrier and thus the electrons stored in this floating gate are eliminated.
Various alternatives of such EPROM cells have been devised. Some of these alternatives are illustrated in FIGS. 1B-1D.
FIG. 1B differs from FIG. 1A by the doping level of the source region. This doping is progressive so that the source-substrate junction can withstand a relatively high voltage. This cell is electrically erasable by applying a high voltage to the source whereas the control gate is grounded and the drain is floating.
A drawback of the erasing mode lies in that, if the erasing time duration is too long, an electron depletion may occur in the floating gate which is then positively charged instead of returning to a neutral state. The channel may then be permanently conductive and, during a reading step, it is no longer possible to identify a conductive cell. Various circuits have been devised to avoid this drawback.
FIG. 1C illustrates a structure to avoid the above mentioned drawback. The floating gate GF coats only a portion of the channel length so that, even if the floating gate GF remains slightly positively charged, there is still a blocked channel region. However, this structure requires an increased cell surface.
FIG. 1D represents a further alternative described in an article by Mizutani and Makita in IEEE Transactions on Electron Devices, Vol. ED-34, No. 6, June 1987, pp 1297-1303 and in Japanese application 62/215079. In this structure, the floating gate coats only a portion of the channel region and is not coated with the control gate. The above article describes an implementation of this floating gate using a polysilicon spacer formed on one side of the control gate.
The above described FIGS. 1A-1D are very schematic and the existing devices exhibit many alternatives with respect to what has been described, especially regarding the shape of the source and drain regions, of the LDD type or not, of the doping gradient type (as represented in FIG. 1B) or not, and the connections. More particularly, in FIGS. 1A-1D, a source metallization and a drain metallization are represented over each source and drain region. Conventionally in a memory array, the various memory cells have a common source. Then, no metallization source is provided on each cell.
EPROM cells, wherein the floating gate extends not only above the channel but also above a low doped extension of the source and/or drain adjacent to the channel, are also known in the art (cf. Japanese application 1/262 669; U.S. Pat. Nos. 4,804,637, 4,203,158, 5,267,194, 5,202,576; European application 5 977 722; German application 3 345 173; and IEEE Electron Device Letters (Vol. 11, No. 11, Nov. 1990, pp. 514-516). In most of these documents, the floating gate and the control gate are at least partially stacked.
FIG. 9 of U.S. Pat. No. 4,754,320 shows an EPROM cell wherein the floating gate is lateral with respect to the control gate and extends above a low doped extension of the device. The thicknesses of the insulating material under the control gate and the floating gate are equal and the charging of the floating gate results from hot carrier injection.
Considering the operation of the above-described memory cells, in all these cells, hot carriers generated in the channel will have an effect in at least one of the operating modes. All these cells exhibit at least two of the following drawbacks.
1. At each read operation, hot carriers are unavoidably generated in the channel, near the drain, and a spurious injection of carriers (electrons) occurs in the gate. As a result, a charge accumulation in the floating gates occurs and the non-programmed cells look, after several read operations, like programmed cells. In other words, the threshold voltages of the programmed cells and non-programmed cells get closer and become more difficult to differentiate.
2. The programming operation requires the flow of a relatively high current between the source and the drain with, for example, a 12-volt voltage. In conventional integrated circuits, means are known for providing from a low supply voltage (for example 3 or 5 volts) a higher voltage (approximately 12 volts). These systems are called charge pumps. However, a drawback of charge pumps is that they have high output impedances and therefore are not adapted to conduct high currents.
Therefore, a high voltage supply external to the integrated circuit must be provided for the programming step.
3. The programming and erase operations are binary operations. These cells are not adapted to store analog values.
Other drawbacks are particularly related to EEPROM cells, that is, cells having a source region with a specific diffusion profile such as illustrated in FIG. 1B. These drawbacks are described as follows.
4. Given, the type of formation of the source regions, and, as the case may be, the drain regions, the diffusion depth of the doping atoms of the source beneath the gate is not properly controlled; therefore, the effective length of the channel region is variable, which affects the threshold voltage.
5. The injection of hot carriers in the gate during the erase operation at high voltages can degrade the gate oxide. These cells therefore are fragile.
6. As above mentioned, there is a risk that the polarity of the floating gates may be inverted, which requires providing necessary steps so that the cells are not permanently conductive.